One problem that needs to be overcome in any digital data system is how to synchronize the timing reference of the receiver with the timing reference of the incoming data. Hence, in such a system it is desirable to provide a bit sync signal with the synchronous digital information to be used in decoding the transmitted digital information. Generally, a bit sync signal is usually provided by a predetermined number of preamble bits in a form of a preamble word which precedes a digital message. The preamble word is usually an alternating one and zero pattern to synchronize the internal clock of the receiver to that of the received signal, as quickly as possible.
The data information for radio transmission and reception is encoded. Thus, the encoded information can be of the type of scrambled speech, digital data, or any other form of data transfer. A type of frequency-shift keying (FSK) commonly referred to as minimum-shift keying (MSK) is particularly well suited for use in radio communications systems since the spectral energy is more easily contained within the limited bandwidth available than other binary frequency or phase-shift-keying modulations.
MSK modulation encodes the data bits as frequency shifts of the signal at time intervals equal to 1/(baud rate) where the baud rate is the transmission speed. The start of each new modulated bit is referred to as a bit boundary. An MSK signal is a continuous-phase-frequency-shift-keying (CPFSK). This implies that the phase of an MSK signal is continuous across the bit boundaries. For example, a mark or binary one may be characterized by modulation with a 1200 Hz signalling tone, and a space or binary zero may be characterized by modulation with an 1800 Hz signalling tone. The continuous phase in CPFSK indicates that the phase at frequency changes between the two signalling tones is continuous, i.e., a signalling tone begins at the same phase that the previous signalling tone ended with. In the preferred embodiment of the instant invention, the modulation technique is comprised of minimum shift keying (MSK) of digital data.
Also, to be MSK, the deviation ratio of the CPFSK must be equal to one-half. The deviation ratio is the frequency difference between the two signalling tones divided by the rate of transmission of the bits expressed in bits per second. In the above example of CPFSK with signalling tones of 1200 HZ and 1800 Hz, the transmission speed would be 1200 bits per second to be MSK. The MSK encoding scheme then sends out data at this constant rate, or transmission speed, which is referred to as the baud rate.
On the other end, an MSK decoder or demodulator will attempt to recover the data information from the transmitted signal. For data recovery, the decoder needs to synchronize to the transmitted data signal. This implies some kind of clock recovery scheme or mechanism in the decoder.
The clock recovery portion may be a phase-lock-loop which is synchronized to the bit transitions or boundaries of the preamble word previously mentioned. The demodulator is thus provided with an internal clock in the form of a phase-lock-loop that is based on a frequency which is a multiple of the expected preamble or incoming bit stream and is thus phase-locked to the incoming data for subsequent decoding or detecting.
Thus, the conventional demodulator consists of two parts: a device which extracts the bit clock, and a detector which recovers the original transmitted data.
An MSK demodulator can be built with varying amounts of hardware. As the knowledge of the synchronization clock of the transmitted signal becomes more exact, the reliability of the signal detection increases. Thus, better reliability in detection results in better performance, especially in poor signal to noise environments. Typically, the more reliable the demodulator becomes, the more hardware or complexity is required. However, the faster the transmission rate, or the more complex the demodulator, the higher the cost of implementation.
For example, in the microprocessor-based MSK demodulator such as described in U.S. Pat. No. 4,669,095, assigned to the assignee of the present invention, which is hereby incorporated by reference, a large portion of the processor time is used just in trying to derive a synchronization signal to recover the transmitter time base clock. Accordingly, there exists a need to conserve processor steps, or in other ways to simplify the demodulator while providing reliable signal detection.